View AST1S31HF_9123227.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. september 2014 docid026968 rev 1 1/29 AST1S31HF up to 4 v, 3 a step-down 2. 3 mhz switching regulator for automotive applications datasheet - production data features ? aecq100 qualified ? 3 a dc output current ? 2.8 v to 4 v input voltage ? output voltage adjustable from 0.8 v ? 2.3 mhz switching frequency ? internal soft-start and enable ? integrated 70 m ? and 55 m ? power mosfets ? all ceramic capacitor ? power good (por) ? cycle-by-cycle current limiting ? current foldback short-circuit protection ? vfdfpn 3 x 3 - 8l package applications ? designed for automotive systems ? battery powered applications ? car body applications description the AST1S31HF is an in ternally compensated 2.3 mhz fixed frequency pwm synchronous step- down regulator. the AST1S31HF operates from 2.8 v to 4 v input, while it regulates an output voltage as low as 0.8 v and up to v in . the AST1S31HF device integrates a 70 m ? high- side switch and a 55 m ? synchronous rectifier allowing very high efficiency with very low output voltages. the peak current mode control with internal compensation deliver a very compact solution with a minimum component count. the AST1S31HF is available in a 3 mm x 3 mm, 8-lead vfdfpn package. figure 1. application circuit vinsw sw vfb pg gnd en AST1S31HF cin_sw cout l r1 r2 vina cin_a r3 vout vin www.st.com
contents AST1S31HF 2/29 docid026968 rev 1 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 datasheet parameters over the temperatur e range . . . . . . . . . . . . . . . . 8 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.4 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5 enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6 light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.7 hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4 thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5 layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
docid026968 rev 1 3/29 AST1S31HF contents 29 10 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
pin settings AST1S31HF 4/29 docid026968 rev 1 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description table 1. pin description no. type description 1 vina unregulated dc input voltage 2en enable input. with en higher than 1.5 v the device in on and with en lower than 0.5 v the device is off. 3fb feedback input. connecting the output voltage directly to this pin the output voltage is regulated at 0.8 v. to have higher regulated voltages an external resistor divider is required from vout to the fb pin. 4 agnd ground 5pg open drain power good (por) pin. it is released (open drain) when the output voltage is higher than 0.92 * v out with a delay of 170 ? s. if the output voltage is below 0.92 * v out , the por pin goes to low impedance immediately. if not used, it can be left floating or to gnd. 6 vinsw power input voltage 7 sw regulator output switching pin 8 pgnd power ground 9 epad exposed pad connected to ground
docid026968 rev 1 5/29 AST1S31HF maximum ratings 29 2 maximum ratings stressing the device above the rating listed in table 2: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. table 2. absolute maximum ratings symbol parameter value unit v in input voltage -0.3 to 5 v v en enable voltage -0.3 to v in v sw output switching voltage -1 to v in v pg power-on reset voltage (power good) -0.3 to v in v fb feedback voltage -0.3 to 1.5 p tot power dissipation at t a < 60 c 2.25 w t op operating junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c
thermal data AST1S31HF 6/29 docid026968 rev 1 3 thermal data table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction ambient (1) 1. package mounted on demonstration board. vfdfpn 60 c/w
docid026968 rev 1 7/29 AST1S31HF electrical characteristics 29 4 electrical characteristics t j = -40 c to 125 c, v in = 4 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test condition values unit min. typ. max. v in operating input voltage range 2.8 4 v v inon turn-on v cc threshold 2.3 2.45 2.6 v inoff turn-off v cc threshold 1.85 2.0 2.15 r dson -p high-side switch on-resistance i sw = 300 ma, t j = 25 c 70 110 m ? i sw = 300 ma 140 r dson -n low-side switch on- resistance i sw = 300 ma, t j = 25 c 55 90 m ? i sw = 300 ma 110 i lim maximum limiting current 3.6 6.0 a oscillator f sw switching frequency 1.75 2.3 2.5 mhz dynamic characteristics v fb feedback voltage i load = 0 a 0.79 0.8 0.81 v dc characteristics i q quiescent current duty cycle = 0, no load v fb = 1.2 v 630 1200 ? a i qst-by total standby quiescent current off 1 ? a enable v en en threshold voltage device on level 1.5 v device off level 0.5 i en en current 0.1 ? a power good pg pg threshold 92 94 96 %v fb mv pg output voltage low isink = 6 ma open drain 400 pg rise delay 170 ? s soft-start t ss soft-start duration 400 ? s protection t shdn thermal shutdown (1) 150 c hystereris (1) 20 1. guaranteed by design.
datasheet parameters over the temperature range AST1S31HF 8/29 docid026968 rev 1 5 datasheet parameters ov er the temperature range the 100% of the population in the production flow is tested at three different ambient temperatures (-40 c, +25 c, +125 c) to gu arantee the datasheet parameters inside the junction temperature range (-40 c, +125 c). the device operation is guaranteed when the junction temperature is inside the (-40 c, +125 c) temperature range. the desi gner can estimate the s ilicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation. however the embedded thermal protection disabl es the switching activity to protect the device in case the junction temperature reaches the tshdn (+150 c typ.) temperature. all the datasheet parameters can be guarant eed to a maximum junction temperature of +125 c to avoid triggering the thermal shutdown protection during the testing phase because of self-heating.
docid026968 rev 1 9/29 AST1S31HF functional description 29 6 functional description the AST1S31HF device is based on a ?peak cu rrent mode?, constant frequency control. the output voltage v out is sensed by the feedback pin (fb) compared to an internal reference (0.8 v) providing an error signal tha t, compared to the output of the current sense amplifier, controls the on and off time of the power switch. the main internal blocks are shown in the block diagram in figure 3 . they are: ? a fully integrated osc illator that provides th e internal clock and th e ramp for the slope compensation avoiding sub-harmonic instability ? the soft-start circuitry to limit the inrush current during the start-up phase ? the transconductance error amplifier ? the pulse width modulator and the relative logic circuitry necessary to drive the internal power switches ? the drivers for embedded p-channel and n-channel power mosfet switches ? the high-side current sensing block ? the low-side current sense to implement diode emulation ? the voltage monitor circuitry (uvlo) that checks the input and internal voltages ? the thermal shutdown block, to prevent the thermal runaway. figure 3. block diagram
functional description AST1S31HF 10/29 docid026968 rev 1 6.1 output voltage adjustment the error amplifier reference voltage is 0.8 v typical. the output voltage is adjusted according to the following formula (see figure 1 on page 1 ): equation 1 to assure working on the low noise mode, with the nominal switching frequency, the maximum duty cycle allowed is 80% typical. if a bigger duty cycle is required, the device can reduce the switching frequency to one half of the nominal switching frequency. 6.2 soft-start the soft-start is essential to assure the correct and safe start-up of the step-down converter. it avoids the inrush current surge and makes the output voltage rise monothonically. the soft-start is managed ramping the reference of the error amplifier from 0 v to 0.8 v. the internal soft-start capacitor is charged with a resistor to 0.8 v, then the fb pin follows the reference so that the output voltage is regu lated to rise to the set value monothonically. 6.3 error amplifier and control loop stability the error amplifier provides the error signal to be compared with the high-side switch current through the current sense circuitry. th e non-inverting input is connected with the internal 0.8 v reference, whils t the inverting input is the fb pin. the compensation network is internal and connected be tween the e/a output and gnd. the error amplifier of the AST1S31HF is a transconductance operational amplifier, with high bandwidth and high output impedance. v out 0.8 1 r 1 r 2 ------ - + ?? ?? ? = table 5. characteristics of the uncompensated error amplifier description value dc gain 87 db gm 236 ? a/v ro 98 m ?
docid026968 rev 1 11/29 AST1S31HF functional description 29 the AST1S31HF device embeds th e compensation network that assures the stability of the loop in the whole operating range. in section 6.7 on page 17 all the tools needed to check the loop stability are shown. in figure 4 is shown the simple small signal model for the peak current mode control loop. figure 4. block diagram of the loop for the small signal analysis three main terms can be identified to obtain the loop transfer function: 1. from control (output of e/a) to output, g co (s) 2. from output (vout) to the fb pin, g div (s) 3. from the fb pin to control (output of e/a), g ea (s). the transfer function from control to output g co (s) results: equation 2 where r load represents the load resistance, r i the equivalent sensing resistor of the current sense circuitry (0.38 ? ), ? p the single pole introduced by the lc filter and ? z the zero given by the esr of the output capacitor. f h (s) accounts the sampling effect performed by the pwm comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. l cout curr ent sense logic and driver slope compensation pw m com parator error amp rc cc r1 r2 0.8 v high side switch low side switch g co (s) g div (s) g ea (s) vin v c v out v fb g co s ?? r load r i ----------------- - 1 1 r out t sw ? l --------------------------- - m c 1d ? ?? 0.5 ? ? ?? ? + -------------------------------------------------------------------------------------------- - 1 s ? z ------ + ?? ?? 1 s ? p ------ + ?? ?? --------------------- - f h s ?? ??? =
functional description AST1S31HF 12/29 docid026968 rev 1 equation 3 equation 4 where: equation 5 s n represents the on time slope of the sensed inductor current, s e the slope of the external ramp (v pp peak-to-peak amplitude - 0.55 v) that implements the slope compensation to avoid sub-harmonic oscillations at the duty cycle over 50%. the sampling effect contribution f h (s) is: equation 6 where: equation 7 and: equation 8 the resistor to adjust the output voltage gives the term from output voltage to the fb pin. g div (s) is: equation 9 ? z 1 esr c out ? ------------------------------- = ? p 1 r load c out ? ------------------------------------- - m c 1d ? ?? 0.5 ? ? lc out f sw ?? --------------------------------------------- + = m c 1 s e s n ------ + = s e v pp f sw ? = s n v in v out ? l ----------------------------- - r i ? = ? ? ? ? ? ? ? ? f h s ?? 1 1 s ? n q p ? ------------------ - s 2 ? n 2 ------ ++ ------------------------------------------ - = q p 1 ? m c 1d ? ?? 0.5 ? ? ?? ? ---------------------------------------------------------- = ? n ? f sw ? = g div s ?? r 2 r 1 r 2 + -------------------- =
docid026968 rev 1 13/29 AST1S31HF functional description 29 the transfer function from fb to vc (output of e/a) introduces the singularities (poles and zeroes) to stabilize the loop. in figure 5 the small signal model of the error amplifier with the internal compensation network is shown. figure 5. small signal model for the error amplifier r c and c c introduce a pole and a zero in the open loop gain. c p does not significantly affect system stability and can be neglected. so g ea (s) results: equation 10 where g ea = g m r o . the poles of this transfer function are (if c c >> c 0 + c p ): equation 11 equation 12 whereas the zero is defined as: equation 13 the embedded compensation network is r c = 80 k ? , c c = 55 pf while c p and c o can be considered as negligible. the error amplifier output resistance is 98 m ?? so the relevant singularities are: equation 14 co ro cc cc cp gm*vd v fb v ref vd rc g ea s ?? g ea0 1s + r c c c ?? ?? ? s 2 r 0 c 0 c p + ?? r c c c sr 0 c c ? r 0 c 0 c p + ?? r c c c ? + ? + ?? 1 + ? + ?? ?? ------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------- = f p lf 1 2 ? r 0 c c ?? ? --------------------------------- - = f p hf 1 2 ? r c c 0 c p + ?? ?? ? ---------------------------------------------------- = f z 1 2 ? r c c c ?? ? --------------------------------- = f z 36 2 khz ? = f p lf 13 6 hz ? =
functional description AST1S31HF 14/29 docid026968 rev 1 so closing the loop the loop gain g loop (s) is: equation 15 example: vin = 3.3 v, vout = 1.2 v, iomax = 3 a, l = 0.91 ? h, cout = 22 ? f (mlcc), r1 = 100 k ? , r2 = 200 k ?? (see section 7.2 on page 19 and section 7.3 on page 20 for inductor and output capacitor selection guidelines). the module and phase bode plot are reported in figure 6 . the bandwidth is 230 khz and the phase margin is 70 degrees. figure 6. module and phase bode plot g loop s ?? g co s ?? g div s ?? g ea s ?? ?? = 0.1 1 10 100 110 3 ? 110 4 ? 110 5 ? 110 6 ? 110 7 ? 60 ? 42 ? 24 ? 6 ? 12 30 48 66 84 102 120 frequency [hz] module [db] 0.1 1 10 100 110 3 ? 110 4 ? 110 5 ? 110 6 ? 110 7 ? 210 ? 182.5 ? 155 ? 127.5 ? 100 ? 72.5 ? 45 ? 17.5 ? 10 frequency [hz] phase
docid026968 rev 1 15/29 AST1S31HF functional description 29 6.4 overcurrent protection the ast1s31 device implements overcurrent pr otection sensing the current flowing through the high-side current switch. if the current exceeds the overcurrent threshold the high-side is turned off, implementing cycle-by-cycle current limit ation. since the regulation loop is no more fixing the duty cycle, the output voltage is unregulated and the fb pin falls accordingly to the new duty cycle. the mechanism to adjust the switching under the current foldback condition exploits the low-side current sense circuitry. if fb is lower than 0.2 v, the high-side power mosfet is turned off after the minimum conduction time (approximately 100 nsec typ.), then, after a proper deadtime that avoids the cross conduction, the low-side is turned on until the low-side current is lower than a valley threshold (1.5 a typ.). once the low-side is turned of f the high-side is immediately turned on. in this way the frequency is adjusted to keep the inductor current ripple between peak current value that could be evaluated with the following equation: equation 16 where dcr l is the series resistance of the indu ctor and the measured value of the valley current threshold (1.5 a typ.), so properly limiting the ou tput current in case of the overcurrent or short-circuit . the overcurrent protection is always effectiv e when vfb < 0.2 v thanks to the natural frequency reduction. no frequency foldback is otherwise implemented when vfb > 0.2 v. in this case, when the current ripple during the on p hase is bigger than the one during the of f phase, there will be a peak current level higher than the current limit threshold. the following equations show the inductor curren t ripple during the on and off phases in case of overcurrent condition: on phase: equation 17 where: equation 18 i peak i valley v in v out dcr l r ds on ?? hs + ?? i valley ? ? + l --------------------------------------------------------------------------------------------------------------- - t onmin ?? ? + = ? i ton v in v out ? dcr l r ds on ?? hs + ?? i ? ? l ------------------------------------------------------------------------------------------------ - t onmin ?? ? = v out v fb v outset 0.8 ---------------------- ? =
functional description AST1S31HF 16/29 docid026968 rev 1 it?s also possible define the output voltage in function of input voltage, on phase time and switching frequency: equation 19 so the on phase the equation results: equation 20 off phase: equation 21 it is possible to repeat the considerations realiz ed to the on phase equation. so it's possible to write the off phase equation in the following manner: equation 22 the peak current escalates over the peak current threshold (called ?ocp1?) if : equation 23 in case the current es calates up to a further current threshold (called ?ocp2?), slightly higher than ocp1, the converter stops the switching activity, the reference of the error amplifier is pulled down and then it restarts with a new soft-start procedure. if the overcurrent condition is still active, the current foldback with frequency redu ction properly limit the output current. v outset v in d min ? v in t onmin t sw ------------------ - ? == ? i ton v fb ?? v in v fb v in t onmin ? 0.8 t sw ? ---------------------------------- - ? ? dcr l r ds on ?? highside + ?? i ? ? l ------------------------------------------------------------------------------------------------------------------------------- -------------------------- - t onmin ? = ? i toff r ds on ?? lowside dcr l + ?? iv out ? ? ? l ------------------------------------------------------------------------------------------------------ - t sw ? = ? i toff v fb ?? r ds on ?? lowside dcr l + ?? iv fb v in t onmin ? 0.8 t sw ? ---------------------------------- - ? ? ? ? l ------------------------------------------------------------------------------------------------------------------------------- ------------- t sw ? = ? i ton v fb ??? i toff v fb ?? ?
docid026968 rev 1 17/29 AST1S31HF functional description 29 figure 7. overcurrent protection region 6.5 enable function the enable feature allows to put the device in to the standby mode. with the en pin lower than 0.4 v, the device is disabled and the pow er consumption is reduced to less than 10 ? a. with the en pin higher than 1.2 v, the device is enabled. if the en pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also v in compatible. 6.6 light-load operation with the peak current mode control loop the out put of the error amplifier is proportional to the load current. the AST1S31HF increases light-load efficiency, when the output of the error amplifier falls below a certain threshold, the high-side turn-on is prevented. this mechanism reduces the switching frequency at the light-load in order to save the switching losses. 6.7 hysteretic thermal shutdown the thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 o c. once the junction temperature goes back to about 130 o c, the device restarts into the normal operation.
application information AST1S31HF 18/29 docid026968 rev 1 7 application information 7.1 input capacitor selection the capacitor connected to the input must be capable to support the maximum input operating voltage and the maximum rms input current required by the device. the input capacitor is a subject of a pulsed current, the rms value of which is dissipated over its esr, affecting the overa ll system efficiency. so the input capacitor must have an rms current rating higher than the maximum rms input current and an esr value compliant with the expected efficiency. the maximum rms input current flowing through the capacitor can be calculated as: equation 24 where i o is the maximum dc output current, d is the duty cycle, and ? ? is the efficiency. considering ?? = 1, this function has a maximum at d = 0.5 and is equal to i o /2. the peak-to-peak voltage across the input capacitor can be calculated as: equation 25 where esr is the equivalent series resistance of the capacitor. given the physical dimension, ceramic capaci tors can well meet the requirements of the input filter sustaining a higher input rms curren t than electrolytic / tantalum types. in this case the equation of c in as a function of the target peak-to-peak voltage ripple (v pp ) can be written as follows: equation 26 neglecting the small esr of ceramic capacitors. considering ?? = 1, this function has its maximum in d = 0.5, therefore, given the maximum peak-to-peak input voltage (v pp_max ), the minimum input capacitor (c in_min ) value is: equation 27 typically, c in is dimensioned to keep the maximum peak -to-peak voltage ripple in the order of 1% of v inmax . i rms i o d 2d 2 ? ? -------------- - ? d 2 ? 2 ------ - + ? = v pp i o c in f sw ? ------------------------- 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? esr i o ? + ? = c in i o v pp f sw ? -------------------------- - 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? ? = c in_min i o 2v pp_max f sw ?? ----------------------------------------------- - =
docid026968 rev 1 19/29 AST1S31HF application information 29 the placement of the input capacitor is very important to avoid noise injection and voltage spikes on the input voltage pin. so the c in must be placed as close as possible to the vin_sw pin. in table 6 some multilayer ceramic capacitors suitable for this device are given. a ceramic bypass capacitor, as close as possible to the vina pin so that additional parasitic esr and esl are minimized, is suggested in order to prevent inst ability on the output voltage due to noise. the value of the bypass capacitor can go from 330 nf to 1 f. 7.2 inductor selection the inductance value fixes the current ripple flowing through the output capacitor. so the minimum inductance value to have the expected current ripple must be selected. the rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. in the continuous current mode (ccm), th e inductance value can be calculated by equation 28 : equation 28 where t on is the conduction time of the high-side switch and t off is the conduction time of the low-side switch [in ccm, f sw = 1 / (t on + t off )]. the maximum current ripple, given the v out , is obtained at maximum t off , that is, at a minimum du ty cycle (see previous section to calculate minimum duty). so by fixing ? i l = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: equation 29 where f swmin is the minimum switching frequency, according to table 4 on page 7 . the slope compensation, to prevent the sub-harmonic instability in the peak current control loop, is internally managed and so fi xed. this implies a fu rther lower limit for the inductor value. to assure sub-harmonic stability: equation 30 where v pp is the peak-to-peak value of the slope compensation ramp. the inductor value selected based on equation 29 must satisfy equation 30 . table 6. input mlcc capacitors manufacturer series cap value ( f) rated voltage (v) murata gcm 47 6.3 tdk cga6 47 6.3 taiyo yuden lmk325 47 10 ? i l v in v out ? l ----------------------------- - t on ? v out l -------------- t off ? == l min v out ? i max ---------------- 1d min ? f swmin ---------------------- - ? = lv out 2v pp f sw ?? ?? ? ?
application information AST1S31HF 20/29 docid026968 rev 1 the peak current through the inductor is given by equation 31 : equation 31 so if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. the higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. in table 7 some inductor part numbers are listed. 7.3 output capacitor selection the current in the output capacitor has a triangular waveform which generates a voltage ripple across it. this ripple is due to the ca pacitive component (charge or discharge of the output capacitor) and the resistive component ( due to the voltage drop across its esr). so the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. the amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. equation 32 for a ceramic (mlcc) capacitor, the capaciti ve component of the ripple dominates the resistive one. while for an electrol ytic capacitor the opposite is true. as the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. the equations of section 6.3 on page 10 help to check loop stab ility given the application conditions, the value of the inductor and of the output capacitor. in table 8 some capacitor series are listed. table 7. inductors manufacturer series inductor value ( h) saturation current (a) coiltronics dra73 0.6 to 2.2 5.5 to 7.9 coilcraft xal40xx 0.6 to 2.2 5.4 to 8.35 i lpk ? i o ? i l 2 -------- + = table 8. output capacitors manufacturer series cap value ( f) rated voltage (v) esr (m ? ) murata gcm 22 to 470 10 5 tdk cga6 22 to 470 16 10 ? v out esr ? i max ? ? i max 8c out f sw ?? ------------------------------------ - + =
docid026968 rev 1 21/29 AST1S31HF application information 29 7.4 thermal dissipation the thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 c. the three differ ent sources of losses within the device are: a) conduction losses due to the on-resistance of the high-side switch (r hs ) and low- side switch (r ls ); these are equal to: equation 33 where d is the duty cycle of the application. note that the duty cycle is theoretically given by the ratio between v out and v in , but it is actually slightly hi gher to compensa te the losses of the regulator. b) switching losses due to the high-side power mosfet turn-on and turn-off; these can be calculated as: equation 34 where t rise and t fall are the overlap times of the voltage across the high-side power switch (v ds ) and the current flowing into it during the turn-on and turn-off phases, as shown in figure 8 . t sw is the equivalent switching time. fo r this device the typical value for the equivalent switching time is 20 ns. c) quiescent current lo sses, calculated as: equation 35 where i q is the quiescent current (i q = 1.2 ma maximum). the junction temperature t j can be calculated as: equation 36 where t a is the ambient temperature and p tot is the sum of the power losses just seen. rth ja is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. for this device the path through the exposed pa d is the one conducting the largest amount of heat. the rth ja measured on the demonstration board (see figure 11 on page 25 ) is about 60 c/w. p cond r hs i out 2 dr ls i out 2 1d ? ?? ?? + ?? = p sw v in i out t rise t fall + ?? 2 ------------------------------------------ - fsw ?? ? v in i out t sw f sw ??? == p q v in i q ? = t j t a rth ja p tot ? + =
application information AST1S31HF 22/29 docid026968 rev 1 figure 8. switching losses 7.5 layout consideration the pc board layout of the switching dc-dc re gulator is very important to minimize the noise injected in high impedance nodes, to reduce interference generated by the high switching current loops and to optim ize the reliability of the device. in order to avoid emc problems, the high switching current loops must be as short as possible. in the buck converter there are two high switching current loops: during the on- time, the pulsed current flows through the input capacitor, the high-side power switch, the inductor and the output capacitor; during the of f-time through the low- side power switch, the inductor and the output capacitor. the input capacitor connected to vinsw must be placed as close as possible to the device, to avoid spikes on vinsw due to the st ray inductance and the pulsed input current. in order to prevent the dynamic unbalance between vinsw and vina, the trace connecting the vina pin to the input must be derived from vinsw. the feedback pin (fb) connection to the external resistor divider is a high impedance node, so the interference can be minimized by rout ing the feedback node with a very short trace and as far as possible from the high current paths. a single point connection from signal gr ound to power ground is suggested. thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large gr ound plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion. v sw i sw,hs v in v ds,hs p cond,hs p cond,ls p sw t fall t rise am11422v1
docid026968 rev 1 23/29 AST1S31HF application information 29 figure 9. pcb layout example am11423v1 input cap as close as possible to vinsw pin star center for common ground short fb trace vina derived from cin to avoid dynamic voltage drop between vina and vinsw short high switching current loop via to connect the thermal pad to bottom or inner ground plane
demonstration board AST1S31HF 24/29 docid026968 rev 1 8 demonstration board figure 10. demonstration board schematic AST1S31HF u1 fb 3 agnd 4 vin_sw 6 vin_a 1 en 2 sw 7 pgnd 8 epad 9 pgood 5 vin c3 1uf c1 47uf l1 0.91uh r3 10k r1 100k r2 200k c2 22uf vout table 9. component list reference part number de scription manufacturer u1 AST1S31HF stm l1 dra73 1r0 r 0.91 h, isat = 8.22 a coiltronics c1 gcm32er70j476me16 47 f 6.3 v x7r murata c2 gcm32er71a226ke12 22 f 10 v x7r murata c3 1 f 25 v x7r c4 nc r1 100 k ?? 1% r2 200 k ? 1% r3 10 k ? 1%
docid026968 rev 1 25/29 AST1S31HF demonstration board 29 figure 11. demonstration board pcb top and bottom, dfn package
package information AST1S31HF 26/29 docid026968 rev 1 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark.
docid026968 rev 1 27/29 AST1S31HF package information 29 figure 12. vfdfpn8 (3 x 3 x 1.0 mm) package outline table 10. vfdfpn8 (3 x 3 x 1.0 mm) package mechanical data symbol dimensions (mm) dimensions (inch) min. typ. max. min. typ. max. a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0.0 0.05 0.0 0.0020 b 0.25 0.30 0.35 0.0098 0.0118 0.0138 d 3.00 0.1181 d2 2.234 2.384 2.484 0. 0878 0.0937 0.0976 e 3.00 0.1181 e2 1.496 1.646 1.746 0. 0589 0.0648 0.0687 e 0.65 0.0256 l 0.30 0.40 0.50 0.0118 0.0157 0.0197
order codes AST1S31HF 28/29 docid026968 rev 1 10 order codes 11 revision history table 11. ordering information order code package AST1S31HF vfdfpn 3 x 3 8l table 12. document revision history date revision changes 30-sep-2014 1 initial release.
docid026968 rev 1 29/29 AST1S31HF 29 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of AST1S31HF

	To Download AST1S31HF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .